/*
 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/********************************************************************
* file: cslr_pa_ra.h
*
* Brief: This file contains the Register Description for pa_ra
*
*********************************************************************/
#ifndef CSLR_PA_RA_H_
#define CSLR_PA_RA_H_

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>

#ifdef __cplusplus
extern "C" {
#endif

/* Minimum unit = 1 byte */

/**************************************************************************\
* Register Overlay Structure for HEAP_REGION
\**************************************************************************/
typedef struct  {
    volatile Uint32 LOW; /* This register contains the lower portion of the heap address */
    volatile Uint32 HIGH; /* This register contains the upper portion of the heap address */
} CSL_Pa_raHeap_regionRegs;

/**************************************************************************\
* Register Overlay Structure for FLOW_OVERRIDE
\**************************************************************************/
typedef struct  {
    volatile Uint32 TIMEOUT; /* This register contains override values that are placed on the packet streaming interface when a context associated with Group N times out before a packet is completely re-assembled and the SOP fragment has been received. */
    volatile Uint32 CRITICAL_ERR; /* This register contains override values that are placed on the packet streaming interface when a fragment associated with Group N is received that has some error. */
    volatile Uint32 NON_CRITICAL_ERR; /* This register contains override values that are placed on the packet streaming interface when a fragment associated with Group N is received that has some non-critical error. */
    volatile Uint8 RSVD0[4];
} CSL_Pa_raFlow_overrideRegs;

/**************************************************************************\
* Register Overlay Structure for STATS
\**************************************************************************/
typedef struct  {
    volatile Uint32 PKTS_REASM; /* Packets reassembled */
    volatile Uint32 TOTAL_FRAGS; /* Total fragments processed */
    volatile Uint32 TOTAL_PKTS; /* Total packets processed (both fragments and non-fragments) */
    volatile Uint32 CONTEXT_TIMEOUT_WITH_SOP; /* Context timeouts with SOP */
    volatile Uint32 CONTEXT_TIMEOUT_WITH_SOP_BYTES; /* Context timeouts with SOP byte count */
    volatile Uint32 CONTEXT_TIMEOUT_WITHOUT_SOP; /* Context timeouts without SOP */
    volatile Uint32 CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES; /* Context timeouts without SOP byte count */
    volatile Uint8 RSVD0[8];
    volatile Uint32 OVERLAP_IPV6_DISCARD; /* Overlapping IPv6 discard */
    volatile Uint32 OVERLAP_IPV6_DISCARD_BYTES; /* Overlapping IPv6 discard byte count */
    volatile Uint32 LARGE_PKTS; /* Large packets */
    volatile Uint32 IPV4_TCP_ERR; /* IPv4 TCP error */
    volatile Uint32 FRAG_LEN_ERR; /* Fragment length error */
    volatile Uint32 ILLEGAL_IPV4_IHL; /* Illegal IPv4 IHL error */
    volatile Uint32 ILLEGAL_SMALL_PKT; /* Illegal small packet error */
    volatile Uint32 ILLEGAL_FRAG_LEN; /* Illegal fragment length error */
    volatile Uint32 ALREADY_COMPLETED_DISCARD; /* Already completed discard error */
    volatile Uint32 ALREADY_COMPLETED_DISCARD_BYTES; /* Already completed discard byte count */
    volatile Uint8 RSVD1[20];
} CSL_Pa_raStatsRegs;

/**************************************************************************\
* Register Overlay Structure for DEBUG
\**************************************************************************/
typedef struct  {
    volatile Uint32 INPUT_PARSER; /* Input parser debug */
    volatile Uint32 CONTEXT_LUT; /* Context LUT debug */
    volatile Uint32 ASSEMBLER; /* Assembler debug */
    volatile Uint32 CONTEXT_ID; /* Context ID debug */
    volatile Uint32 CONTEXT_RAM; /* Context RAM debug */
    volatile Uint32 NODE_HEAP; /* Node heap debug */
    volatile Uint32 FETCH_DMA; /* Fetch DMA debug */
    volatile Uint32 VBUS_DMA; /* VBUS DMA debug */
    volatile Uint32 OUTPUT_DMA; /* Output DMA debug */
    volatile Uint32 FORWARD_FIFO; /* Forward FIFO debug */
    volatile Uint32 OUTPUT_FIFO; /* Output FIFO debug */
} CSL_Pa_raDebugRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVISION; /* Revision Register */
    volatile Uint32 CONFIG; /* This register is used to configure the reassembly module */
    volatile Uint32 TOTAL_CONTEXTS; /* This register is used to configure the total number of contexts handled by the RA */
    volatile Uint32 DISCARD_THRESH; /* This register is used to configure the IP reassembly thresholds */
    volatile Uint32 TIMEOUT_VAL; /* This register is used to configure the context timeout value */
    volatile Uint32 TICK_VAL; /* This register is used to configure the tick size */
    volatile Uint32 VBUSM_CONFIG; /* This register is used to configure VBUSM parameters */
    volatile Uint32 HEAP_REGION_THRESH; /* This register is used to configure the reassembly heap */
    CSL_Pa_raHeap_regionRegs HEAP_REGION[2];
    volatile Uint8 RSVD0[16];
    CSL_Pa_raFlow_overrideRegs FLOW_OVERRIDE[2];
    volatile Uint8 RSVD1[48];
    volatile Uint32 CONTEXT_FORCED_TIMEOUT; /* This register controls statistics increments when a context is forced to timeout due to resource limitations. */
    volatile Uint8 RSVD2[12];
    CSL_Pa_raStatsRegs STATS[2];
    volatile Uint8 RSVD3[384];
    CSL_Pa_raDebugRegs DEBUG;
} CSL_Pa_raRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* LOW */

#define CSL_PA_RA_LOW_ADDR_MASK          (0xFFFFFFFFu)
#define CSL_PA_RA_LOW_ADDR_SHIFT         (0x00000000u)
#define CSL_PA_RA_LOW_ADDR_RESETVAL      (0x00000000u)

#define CSL_PA_RA_LOW_RESETVAL           (0x00000000u)

/* HIGH */

#define CSL_PA_RA_HIGH_ADDR_MASK         (0xFFFFFFFFu)
#define CSL_PA_RA_HIGH_ADDR_SHIFT        (0x00000000u)
#define CSL_PA_RA_HIGH_ADDR_RESETVAL     (0x00000000u)

#define CSL_PA_RA_HIGH_RESETVAL          (0x00000000u)

/* TIMEOUT */

#define CSL_PA_RA_TIMEOUT_THREAD_ID_MASK (0x1F000000u)
#define CSL_PA_RA_TIMEOUT_THREAD_ID_SHIFT (0x00000018u)
#define CSL_PA_RA_TIMEOUT_THREAD_ID_RESETVAL (0x00000000u)

#define CSL_PA_RA_TIMEOUT_FLOW_INDEX_MASK (0x00FF0000u)
#define CSL_PA_RA_TIMEOUT_FLOW_INDEX_SHIFT (0x00000010u)
#define CSL_PA_RA_TIMEOUT_FLOW_INDEX_RESETVAL (0x000000FFu)

#define CSL_PA_RA_TIMEOUT_DST_QUEUE_MASK (0x0000FFFFu)
#define CSL_PA_RA_TIMEOUT_DST_QUEUE_SHIFT (0x00000000u)
#define CSL_PA_RA_TIMEOUT_DST_QUEUE_RESETVAL (0x00000FFFu)

#define CSL_PA_RA_TIMEOUT_RESETVAL       (0x00FF0FFFu)

/* CRITICAL_ERR */

#define CSL_PA_RA_CRITICAL_ERR_THREAD_ID_MASK (0x1F000000u)
#define CSL_PA_RA_CRITICAL_ERR_THREAD_ID_SHIFT (0x00000018u)
#define CSL_PA_RA_CRITICAL_ERR_THREAD_ID_RESETVAL (0x00000000u)

#define CSL_PA_RA_CRITICAL_ERR_FLOW_INDEX_MASK (0x00FF0000u)
#define CSL_PA_RA_CRITICAL_ERR_FLOW_INDEX_SHIFT (0x00000010u)
#define CSL_PA_RA_CRITICAL_ERR_FLOW_INDEX_RESETVAL (0x000000FFu)

#define CSL_PA_RA_CRITICAL_ERR_DST_QUEUE_MASK (0x0000FFFFu)
#define CSL_PA_RA_CRITICAL_ERR_DST_QUEUE_SHIFT (0x00000000u)
#define CSL_PA_RA_CRITICAL_ERR_DST_QUEUE_RESETVAL (0x00000FFFu)

#define CSL_PA_RA_CRITICAL_ERR_RESETVAL  (0x00FF0FFFu)

/* NON_CRITICAL_ERR */

#define CSL_PA_RA_NON_CRITICAL_ERR_THREAD_ID_MASK (0x1F000000u)
#define CSL_PA_RA_NON_CRITICAL_ERR_THREAD_ID_SHIFT (0x00000018u)
#define CSL_PA_RA_NON_CRITICAL_ERR_THREAD_ID_RESETVAL (0x00000000u)

#define CSL_PA_RA_NON_CRITICAL_ERR_FLOW_INDEX_MASK (0x00FF0000u)
#define CSL_PA_RA_NON_CRITICAL_ERR_FLOW_INDEX_SHIFT (0x00000010u)
#define CSL_PA_RA_NON_CRITICAL_ERR_FLOW_INDEX_RESETVAL (0x000000FFu)

#define CSL_PA_RA_NON_CRITICAL_ERR_DST_QUEUE_MASK (0x0000FFFFu)
#define CSL_PA_RA_NON_CRITICAL_ERR_DST_QUEUE_SHIFT (0x00000000u)
#define CSL_PA_RA_NON_CRITICAL_ERR_DST_QUEUE_RESETVAL (0x00000FFFu)

#define CSL_PA_RA_NON_CRITICAL_ERR_RESETVAL (0x00FF0FFFu)

/* PKTS_REASM */

#define CSL_PA_RA_PKTS_REASM_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_PKTS_REASM_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_PKTS_REASM_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_PKTS_REASM_INDEX_MASK  (0x00003FFFu)
#define CSL_PA_RA_PKTS_REASM_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_PKTS_REASM_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_PKTS_REASM_RESETVAL    (0x00000000u)

/* TOTAL_FRAGS */

#define CSL_PA_RA_TOTAL_FRAGS_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_TOTAL_FRAGS_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_TOTAL_FRAGS_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_TOTAL_FRAGS_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_TOTAL_FRAGS_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_TOTAL_FRAGS_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_TOTAL_FRAGS_RESETVAL   (0x00000000u)

/* TOTAL_PKTS */

#define CSL_PA_RA_TOTAL_PKTS_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_TOTAL_PKTS_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_TOTAL_PKTS_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_TOTAL_PKTS_INDEX_MASK  (0x00003FFFu)
#define CSL_PA_RA_TOTAL_PKTS_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_TOTAL_PKTS_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_TOTAL_PKTS_RESETVAL    (0x00000000u)

/* CONTEXT_TIMEOUT_WITH_SOP */

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_RESETVAL (0x00000000u)

/* CONTEXT_TIMEOUT_WITH_SOP_BYTES */

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITH_SOP_BYTES_RESETVAL (0x00000000u)

/* CONTEXT_TIMEOUT_WITHOUT_SOP */

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_RESETVAL (0x00000000u)

/* CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES */

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_TIMEOUT_WITHOUT_SOP_BYTES_RESETVAL (0x00000000u)

/* OVERLAP_IPV6_DISCARD */

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_RESETVAL (0x00000000u)

/* OVERLAP_IPV6_DISCARD_BYTES */

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_OVERLAP_IPV6_DISCARD_BYTES_RESETVAL (0x00000000u)

/* LARGE_PKTS */

#define CSL_PA_RA_LARGE_PKTS_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_LARGE_PKTS_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_LARGE_PKTS_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_LARGE_PKTS_INDEX_MASK  (0x00003FFFu)
#define CSL_PA_RA_LARGE_PKTS_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_LARGE_PKTS_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_LARGE_PKTS_RESETVAL    (0x00000000u)

/* IPV4_TCP_ERR */

#define CSL_PA_RA_IPV4_TCP_ERR_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_IPV4_TCP_ERR_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_IPV4_TCP_ERR_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_IPV4_TCP_ERR_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_IPV4_TCP_ERR_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_IPV4_TCP_ERR_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_IPV4_TCP_ERR_RESETVAL  (0x00000000u)

/* FRAG_LEN_ERR */

#define CSL_PA_RA_FRAG_LEN_ERR_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_FRAG_LEN_ERR_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_FRAG_LEN_ERR_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_FRAG_LEN_ERR_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_FRAG_LEN_ERR_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_FRAG_LEN_ERR_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_FRAG_LEN_ERR_RESETVAL  (0x00000000u)

/* ILLEGAL_IPV4_IHL */

#define CSL_PA_RA_ILLEGAL_IPV4_IHL_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_ILLEGAL_IPV4_IHL_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_ILLEGAL_IPV4_IHL_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_IPV4_IHL_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_ILLEGAL_IPV4_IHL_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_ILLEGAL_IPV4_IHL_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_IPV4_IHL_RESETVAL (0x00000000u)

/* ILLEGAL_SMALL_PKT */

#define CSL_PA_RA_ILLEGAL_SMALL_PKT_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_ILLEGAL_SMALL_PKT_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_ILLEGAL_SMALL_PKT_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_SMALL_PKT_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_ILLEGAL_SMALL_PKT_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_ILLEGAL_SMALL_PKT_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_SMALL_PKT_RESETVAL (0x00000000u)

/* ILLEGAL_FRAG_LEN */

#define CSL_PA_RA_ILLEGAL_FRAG_LEN_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_ILLEGAL_FRAG_LEN_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_ILLEGAL_FRAG_LEN_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_FRAG_LEN_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_ILLEGAL_FRAG_LEN_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_ILLEGAL_FRAG_LEN_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_ILLEGAL_FRAG_LEN_RESETVAL (0x00000000u)

/* ALREADY_COMPLETED_DISCARD */

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_RESETVAL (0x00000000u)

/* ALREADY_COMPLETED_DISCARD_BYTES */

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_ALREADY_COMPLETED_DISCARD_BYTES_RESETVAL (0x00000000u)

/* INPUT_PARSER */

#define CSL_PA_RA_INPUT_PARSER_STATE_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_INPUT_PARSER_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_INPUT_PARSER_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_INPUT_PARSER_RESETVAL  (0x00000000u)

/* CONTEXT_LUT */

#define CSL_PA_RA_CONTEXT_LUT_STATE_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_CONTEXT_LUT_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_LUT_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_LUT_RESETVAL   (0x00000000u)

/* ASSEMBLER */

#define CSL_PA_RA_ASSEMBLER_STATE_MASK   (0xFFFFFFFFu)
#define CSL_PA_RA_ASSEMBLER_STATE_SHIFT  (0x00000000u)
#define CSL_PA_RA_ASSEMBLER_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_ASSEMBLER_RESETVAL     (0x00000000u)

/* CONTEXT_ID */

#define CSL_PA_RA_CONTEXT_ID_STATE_MASK  (0xFFFFFFFFu)
#define CSL_PA_RA_CONTEXT_ID_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_ID_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_ID_RESETVAL    (0x00000000u)

/* CONTEXT_RAM */

#define CSL_PA_RA_CONTEXT_RAM_STATE_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_CONTEXT_RAM_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_RAM_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_RAM_RESETVAL   (0x00000000u)

/* NODE_HEAP */

#define CSL_PA_RA_NODE_HEAP_STATE_MASK   (0xFFFFFFFFu)
#define CSL_PA_RA_NODE_HEAP_STATE_SHIFT  (0x00000000u)
#define CSL_PA_RA_NODE_HEAP_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_NODE_HEAP_RESETVAL     (0x00000000u)

/* FETCH_DMA */

#define CSL_PA_RA_FETCH_DMA_STATE_MASK   (0xFFFFFFFFu)
#define CSL_PA_RA_FETCH_DMA_STATE_SHIFT  (0x00000000u)
#define CSL_PA_RA_FETCH_DMA_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_FETCH_DMA_RESETVAL     (0x00000000u)

/* VBUS_DMA */

#define CSL_PA_RA_VBUS_DMA_STATE_MASK    (0xFFFFFFFFu)
#define CSL_PA_RA_VBUS_DMA_STATE_SHIFT   (0x00000000u)
#define CSL_PA_RA_VBUS_DMA_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_VBUS_DMA_RESETVAL      (0x00000000u)

/* OUTPUT_DMA */

#define CSL_PA_RA_OUTPUT_DMA_STATE_MASK  (0xFFFFFFFFu)
#define CSL_PA_RA_OUTPUT_DMA_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_OUTPUT_DMA_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_OUTPUT_DMA_RESETVAL    (0x00000000u)

/* FORWARD_FIFO */

#define CSL_PA_RA_FORWARD_FIFO_STATE_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_FORWARD_FIFO_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_FORWARD_FIFO_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_FORWARD_FIFO_RESETVAL  (0x00000000u)

/* OUTPUT_FIFO */

#define CSL_PA_RA_OUTPUT_FIFO_STATE_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_OUTPUT_FIFO_STATE_SHIFT (0x00000000u)
#define CSL_PA_RA_OUTPUT_FIFO_STATE_RESETVAL (0x00000000u)

#define CSL_PA_RA_OUTPUT_FIFO_RESETVAL   (0x00000000u)

/* REVISION */

#define CSL_PA_RA_REVISION_SCHEME_MASK   (0xC0000000u)
#define CSL_PA_RA_REVISION_SCHEME_SHIFT  (0x0000001Eu)
#define CSL_PA_RA_REVISION_SCHEME_RESETVAL (0x00000001u)

#define CSL_PA_RA_REVISION_MODID_MASK    (0x0FFF0000u)
#define CSL_PA_RA_REVISION_MODID_SHIFT   (0x00000010u)
#define CSL_PA_RA_REVISION_MODID_RESETVAL (0x00000EF2u)

#define CSL_PA_RA_REVISION_REVRTL_MASK   (0x0000F800u)
#define CSL_PA_RA_REVISION_REVRTL_SHIFT  (0x0000000Bu)
#define CSL_PA_RA_REVISION_REVRTL_RESETVAL (0x00000000u)

#define CSL_PA_RA_REVISION_REVMAJ_MASK   (0x00000700u)
#define CSL_PA_RA_REVISION_REVMAJ_SHIFT  (0x00000008u)
#define CSL_PA_RA_REVISION_REVMAJ_RESETVAL (0x00000000u)

#define CSL_PA_RA_REVISION_REVCUSTOM_MASK (0x000000C0u)
#define CSL_PA_RA_REVISION_REVCUSTOM_SHIFT (0x00000006u)
#define CSL_PA_RA_REVISION_REVCUSTOM_RESETVAL (0x00000000u)

#define CSL_PA_RA_REVISION_REVMIN_MASK   (0x0000003Fu)
#define CSL_PA_RA_REVISION_REVMIN_SHIFT  (0x00000000u)
#define CSL_PA_RA_REVISION_REVMIN_RESETVAL (0x00000001u)

#define CSL_PA_RA_REVISION_RESETVAL      (0x4EF20001u)

/* CONFIG */

#define CSL_PA_RA_CONFIG_IPV4_MIN_PKT_SIZE_MASK (0x0000FF00u)
#define CSL_PA_RA_CONFIG_IPV4_MIN_PKT_SIZE_SHIFT (0x00000008u)
#define CSL_PA_RA_CONFIG_IPV4_MIN_PKT_SIZE_RESETVAL (0x00000044u)

#define CSL_PA_RA_CONFIG_LRO_MODE_MASK   (0x00000001u)
#define CSL_PA_RA_CONFIG_LRO_MODE_SHIFT  (0x00000000u)
#define CSL_PA_RA_CONFIG_LRO_MODE_RESETVAL (0x00000000u)
/*----lro_mode Tokens----*/
#define CSL_PA_RA_CONFIG_LRO_MODE_IP_REASM_MODE (0x00000000u)
#define CSL_PA_RA_CONFIG_LRO_MODE_TCP_LRO_MODE (0x00000001u)

#define CSL_PA_RA_CONFIG_RESETVAL        (0x00004400u)

/* TOTAL_CONTEXTS */

#define CSL_PA_RA_TOTAL_CONTEXTS_TOTAL_CONTEXTS_MASK (0x000007FFu)
#define CSL_PA_RA_TOTAL_CONTEXTS_TOTAL_CONTEXTS_SHIFT (0x00000000u)
#define CSL_PA_RA_TOTAL_CONTEXTS_TOTAL_CONTEXTS_RESETVAL (0x00000400u)

#define CSL_PA_RA_TOTAL_CONTEXTS_RESETVAL (0x00000400u)

/* DISCARD_THRESH */

#define CSL_PA_RA_DISCARD_THRESH_CONTEXTS_MASK (0x000007FFu)
#define CSL_PA_RA_DISCARD_THRESH_CONTEXTS_SHIFT (0x00000000u)
#define CSL_PA_RA_DISCARD_THRESH_CONTEXTS_RESETVAL (0x00000400u)

#define CSL_PA_RA_DISCARD_THRESH_NODES_MASK (0x1FFF0000u)
#define CSL_PA_RA_DISCARD_THRESH_NODES_SHIFT (0x00000010u)
#define CSL_PA_RA_DISCARD_THRESH_NODES_RESETVAL (0x00000FFFu)

#define CSL_PA_RA_DISCARD_THRESH_RESETVAL (0x0FFF0400u)

/* TIMEOUT_VAL */

#define CSL_PA_RA_TIMEOUT_VAL_CONTEXT_MASK (0xFFFFFFFFu)
#define CSL_PA_RA_TIMEOUT_VAL_CONTEXT_SHIFT (0x00000000u)
#define CSL_PA_RA_TIMEOUT_VAL_CONTEXT_RESETVAL (0x10000000u)

#define CSL_PA_RA_TIMEOUT_VAL_RESETVAL   (0x10000000u)

/* TICK_VAL */

#define CSL_PA_RA_TICK_VAL_TICK_SIZE_MASK (0x000003FFu)
#define CSL_PA_RA_TICK_VAL_TICK_SIZE_SHIFT (0x00000000u)
#define CSL_PA_RA_TICK_VAL_TICK_SIZE_RESETVAL (0x00000001u)

#define CSL_PA_RA_TICK_VAL_RESETVAL      (0x00000001u)

/* VBUSM_CONFIG */

#define CSL_PA_RA_VBUSM_CONFIG_READ_PRI_MASK (0x00070000u)
#define CSL_PA_RA_VBUSM_CONFIG_READ_PRI_SHIFT (0x00000010u)
#define CSL_PA_RA_VBUSM_CONFIG_READ_PRI_RESETVAL (0x00000007u)

#define CSL_PA_RA_VBUSM_CONFIG_WRITE_PRI_MASK (0x00000700u)
#define CSL_PA_RA_VBUSM_CONFIG_WRITE_PRI_SHIFT (0x00000008u)
#define CSL_PA_RA_VBUSM_CONFIG_WRITE_PRI_RESETVAL (0x00000007u)

#define CSL_PA_RA_VBUSM_CONFIG_BURST_MODE_MASK (0x00000001u)
#define CSL_PA_RA_VBUSM_CONFIG_BURST_MODE_SHIFT (0x00000000u)
#define CSL_PA_RA_VBUSM_CONFIG_BURST_MODE_RESETVAL (0x00000000u)
/*----burst_mode Tokens----*/
#define CSL_PA_RA_VBUSM_CONFIG_BURST_MODE_64_BYTE (0x00000000u)
#define CSL_PA_RA_VBUSM_CONFIG_BURST_MODE_128_BYTE (0x00000001u)

#define CSL_PA_RA_VBUSM_CONFIG_RESETVAL  (0x00070700u)

/* HEAP_REGION_THRESH */

#define CSL_PA_RA_HEAP_REGION_THRESH_REGION0_MASK (0x000007FFu)
#define CSL_PA_RA_HEAP_REGION_THRESH_REGION0_SHIFT (0x00000000u)
#define CSL_PA_RA_HEAP_REGION_THRESH_REGION0_RESETVAL (0x00000400u)

#define CSL_PA_RA_HEAP_REGION_THRESH_RESETVAL (0x00000400u)

/* CONTEXT_FORCED_TIMEOUT */

#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_ENABLE_MASK (0x80000000u)
#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_ENABLE_SHIFT (0x0000001Fu)
#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_ENABLE_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_INDEX_MASK (0x00003FFFu)
#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_INDEX_SHIFT (0x00000000u)
#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_INDEX_RESETVAL (0x00000000u)

#define CSL_PA_RA_CONTEXT_FORCED_TIMEOUT_RESETVAL (0x00000000u)


#ifdef __cplusplus
}
#endif

#endif
